ASML - Physics Senior Design Engineer Wafer Alignment Job in Veldhoven, Netherlands

ASML is one of the world’s leading manufacturers of chip-making equipment.

Our vision is to enable affordable microelectronics that improve the quality of life.

To achieve this, our mission is to invent, develop, manufacture and service advanced technology for high-tech lithography, metrology and software solutions for the semiconductor industry.

ASML's guiding principle is continuing Moore's Law towards ever smaller, cheaper, more powerful and energy-efficient semiconductors. This results in increasingly powerful and capable electronics that enable the world to progress within a multitude of fields, including healthcare, technology, communications, energy, mobility, and entertainment.

ASML - Physics Senior Design Engineer Wafer Alignment Job Description

To contribute to the development of products by designing, creating and testing, (sub-) systems within the restrictions imposed by system specifications, costs and planning considerations.Job Description You will join the Wafer Alignment group and work together with internal and external customers to design, test and qualify wafer alignment solutions to minimize the effect of the dominant contributors in the on product performance budget. This will contain the development of new WA models to minimize the effects of wafer and mark deformations to overlay.You will be responsible for the feasibility study by testing, analyzing and providing recommendations of complex wafer alignment solutions for our newest NXT/NXE systems, as well as application products.A large part of the work is to interact within a dynamic and diverse ASML community. It is essential to you know your stakeholders and dependencies with other projects. This means that you need to have a pro-active approach, strong communicational skills and ambition to identify improvement opportunities. Enjoy, show energy, have the drive of getting people together and make them enthusiastic to reach that improvement goal.

• To propose tests and simulations to identify budget posts and solution options to enable enhanced wafer alignment performance;
• Construct test plans in order to verify feasibility items. Organize and ensure that tests are done;
• Analyze results to verify budget post and possible solutions to improve overlay via alignment;
• Responsible for the proper documentation of feasibility study simulations and test analysis results;
• Functional overview from alignment sensor to usage of the sensor on customer product wafers and the correction mechanisms.

ASML - Physics Senior Design Engineer Wafer Alignment Job Requirements

Technical University, master or PhD in physics, PDeng, or other relevant applied mathematical study, with at least 4 years of relevant work experience in industry. Experience

• In depth theoretical and experimental experience;
• Strong analytical ability with a pragmatic attitude. Helicopter view, broad scope and team-player. Good communicational skills and good knowledge of English.

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