ASML - Design Engineer Wafer Alignment Job in Veldhoven, Netherlands

ASML is one of the world’s leading manufacturers of chip-making equipment.

Our vision is to enable affordable microelectronics that improve the quality of life.

To achieve this, our mission is to invent, develop, manufacture and service advanced technology for high-tech lithography, metrology and software solutions for the semiconductor industry.

ASML's guiding principle is continuing Moore's Law towards ever smaller, cheaper, more powerful and energy-efficient semiconductors. This results in increasingly powerful and capable electronics that enable the world to progress within a multitude of fields, including healthcare, technology, communications, energy, mobility, and entertainment.

ASML - Design Engineer Wafer Alignment Job Description

To contribute to the development of products by designing, creating and testing, (sub-) systems within the restrictions imposed by system specifications, costs and planning considerations.

Job Description
You will join the Wafer Alignment project that will work together with customers to design, test and qualify wafer alignment solutions to minimize the effect of alignment mark asymmetry, which is one of the dominant contributors in the on product performance budget.You will be responsible for testing, analyzing and providing recommendations of complex wafer alignment solutions in cooperation with the customer, and occasionally at the customer side.

The project includes a lot of different competences on alignment including existing and new alignment sensor HardWare.You will be responsible to gather the relevant information over the different projects and negotiate with the other projects to optimize the test specification.

A large part of the work is to interact within a dynamic and diverse ASML community. It is essential to you know your stakeholders and dependencies with other projects. This means that you need to have a pro-active approach, strong communicational skills and ambition to identify improvement opportunities. Enjoy, show energy, have the drive to getting people together and make them enthusiastic to reach that improvement goal.

• To enable enhanced wafer alignment performance - by specifying, integrating, analyzing and supporting the design and applications of alignment performance
• Construct test plans in order to verify wafer grid qualification and calibration tests. Organize and ensure that tests are done.
• Analyze results to verify implementations and define solutions for new calibration and qualification methods to improve overlay
• Responsible for the proper documentation of specifications, design and test analysis results
• Functional overview from alignment sensor to usage of the sensor on customer product wafers and the correction mechanisms

ASML - Design Engineer Wafer Alignment Job Requirements

Technical University, master or PhD in physics, PDeng, or other relevant applied mathematical study, with at least 2 years of relevant work experience.

Experience

• In depth theoretical and experimental experience.
• Strong analytical ability with a pragmatic attitude. Helicopter view, broad scope and team-player. Good communicational skills and good knowledge of English.

ASML - Design Engineer Wafer Alignment Application Information

Please apply using the apply button below and remember, you found this opportunity on www.Qreer.com

Contact Information

RC02657-QR-COM

ASML - Design Engineer Wafer Alignment Summary

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