Sr. Design Rule Engineer - Logic OPC and DTCO Job in San Jose - CA, United States

ASML is one of the world’s leading manufacturers of chip-making equipment.

Our vision is to enable affordable microelectronics that improve the quality of life. To achieve this, our mission is to invent, develop, manufacture and service advanced technology for high-tech lithography, metrology and software solutions for the semiconductor industry.

ASML's guiding principle is continuing Moore's Law towards ever smaller, cheaper, more powerful and energy-efficient semiconductors. This results in increasingly powerful and capable electronics that enable the world to progress within a multitude of fields, including healthcare, technology, communications, energy, mobility, and entertainment.

Working at ASML
We provide the world’s top chipmakers everything they need to create better performing, cheaper semiconductor chips. Simply put: we are an industry leader supporting industry leaders.

As such, you’ll be encouraged to bring your best ideas and act on them. You’ll have the freedom, trust, and support in your field to experiment and solve complex challenges. Things are rarely dull when you’re constantly breaking new ground.

But despite our fast-paced environment at the forefront of tech, we take your work-life balance and wellbeing seriously. A business is only as good as its employees.

So join us, and you’ll be a part of a global collaboration. One that promotes creativity, the inclusion of highly diverse teams, and an exciting and dynamic work environment. Join us, and you’ll be a part of progress.

Sr. Design Rule Engineer - Logic OPC and DTCO Job Description

Introduction
ASML brings together the most creative minds in science and technology to develop lithography machines that are key to producing faster, cheaper, more energy-efficient microchips. We design, develop, integrate, market and service these advanced machines, which enable our customers - the world’s leading chipmakers – to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics. Our headquarters are in Veldhoven, the Netherlands, and we have 18 office locations around the United States including main offices in Wilton, CT, Chandler, AZ and San Jose, CA.

We are proud of bringing together the brightest minds all over the world to tackle the most challenging problems in making faster and smaller chips. As part of our team, you will have the opportunity to go beyond yourself in developing more advanced techniques and push the technology boundaries.
ASML San Jose, CA is an industry leader in computational lithography for integrated circuits.  Our Tachyon platform enables capabilities that address chip design, photomask making and wafer printing for semiconductor manufacturing and the LithoTuner platform enables lithography optimization for ASML’s leading photo lithography tools, known as ‘scanners’.

Job Mission

• Understand patterning requirements of future devices through interactions with key customers
• Understand technology design rule and patterning limits of future devices focused on logic/MPU customers
• Interactions with key US customer for Logic/MPU roadmap and use case development 

• Customer Interface: responsible for the joint development project activities with primarily Logic/MPU customers. These activities involved in working with the lithography process R&D department and DTCO department of the respective customers on the evaluations and optimizations of the patterning methods in support of the future process technology nodes;  
• Device roadmap: responsible for supporting ASML’s foundry/MPU device roadmaps updates through customer communications and technology requirement analysis.

Sr. Design Rule Engineer - Logic OPC and DTCO Job Requirements

 Education

• Requires a Master’s Degree in Science or Engineering. Ph. D preferred or equivalent experience

• Minimum 10 years of experience in the industry at R&D departments
• Good knowledge on Lithography technologies from wafer process to OPC
• Knowledge on process integration and device physics would be preferred

• Fluent on imaging simulations: Hyperlith  or equivalent tool.
• OPC tool use : Capable of OPC, LMC and DRO of Tachyon or equivalent
• Data analysis : Matlab, Python
• Layout handling : Logic Library design  capability would be preferred 

Sr. Design Rule Engineer - Logic OPC and DTCO Application Information

Sr. Design Rule Engineer - Logic OPC and DTCO Summary

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